Integrated Circuit Design

A 1.0GHz single-issue 64-bit powerPC integer processor

Computer Architecture / Structural Control / CMOS Integrated Circuit Design / High Frequency / Microarchitecture / Parallel Computation / Circuit Design / Solid State Devices and Circuits / Logic Design / Parallel Computer / Electrical And Electronic Engineering / Programmable logic array / Integrated Circuit Design / Read Only Memory / Parallel Computation / Circuit Design / Solid State Devices and Circuits / Logic Design / Parallel Computer / Electrical And Electronic Engineering / Programmable logic array / Integrated Circuit Design / Read Only Memory

A Modular Programmable CMOS Analog Fuzzy Controller Chip

Fuzzy Logic / Response Surface Methodology / Digital Control / Fuzzy Inference / Fuzzy Control / Hardware / Power Consumption / Programmable logic controllers / Prototypes / Lattices / Impurities / Function approximation / Fuzzy Controller / Electrical And Electronic Engineering / UNIVERSE OF DISCOURSE / Integrated Circuit Design / Hardware / Power Consumption / Programmable logic controllers / Prototypes / Lattices / Impurities / Function approximation / Fuzzy Controller / Electrical And Electronic Engineering / UNIVERSE OF DISCOURSE / Integrated Circuit Design

Hierarchical top-down design of analog sensor interfaces: from system-level specifications down to silicon

Productivity / System Design / High Level Synthesis / Radiation Detectors / Asic / Design Methodology / Organization of social memory / Top Down / Front end / Integrated Circuit Design / Design Methodology / Organization of social memory / Top Down / Front end / Integrated Circuit Design

A 400MHz S/390 microprocessor

High Frequency / Fixed Point Theory / Power Supply / Cycle Time / Circuit Design / Logic Design / Floating Point / Timing Optimization / Electrical And Electronic Engineering / Power Dissipation / Phase Lock Loop / Integrated Circuit Design / Logic Design / Floating Point / Timing Optimization / Electrical And Electronic Engineering / Power Dissipation / Phase Lock Loop / Integrated Circuit Design

A 400MHz S/390 microprocessor

High Frequency / Fixed Point Theory / Power Supply / Cycle Time / Circuit Design / Logic Design / Floating Point / Timing Optimization / Electrical And Electronic Engineering / Power Dissipation / Phase Lock Loop / Integrated Circuit Design / Logic Design / Floating Point / Timing Optimization / Electrical And Electronic Engineering / Power Dissipation / Phase Lock Loop / Integrated Circuit Design

A 400MHz S/390 microprocessor

High Frequency / Fixed Point Theory / Power Supply / Cycle Time / Circuit Design / Logic Design / Floating Point / Timing Optimization / Electrical And Electronic Engineering / Power Dissipation / Phase Lock Loop / Integrated Circuit Design / Logic Design / Floating Point / Timing Optimization / Electrical And Electronic Engineering / Power Dissipation / Phase Lock Loop / Integrated Circuit Design

New SRAM design using body bias technique for ultra low power applications

Nanoelectronics / Low Power Electronics / Sram / Application Software / Low voltage / Integrated Circuit Design / Threshold Voltage / Integrated Circuit Design / Threshold Voltage

New SRAM design using body bias technique for ultra low power applications

Nanoelectronics / Low Power Electronics / Sram / Application Software / Low voltage / Integrated Circuit Design / Threshold Voltage / Integrated Circuit Design / Threshold Voltage

High-Level verifiable data-path Synthesis for DSP systems

Digital Signal Processing / Hardware Description Languages / Field-Programmable Gate Arrays / High Level Synthesis / Prototyping / Algorithm Design / Estimation / Field Programmable Gate Array / Mathematical Model / IP networks / HDL / Application Specific Integrated Circuit (ASIC) / Integrated Circuit Design / Algorithm Design / Estimation / Field Programmable Gate Array / Mathematical Model / IP networks / HDL / Application Specific Integrated Circuit (ASIC) / Integrated Circuit Design

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

High Frequency / Silicon on Insulator / Bit Error Rate / Jitter / High performance / Phase Locked Loops / Phase Lock Loop / Integrated Circuit Design / Integrated Circuit Packaging / Transceivers / Phase Locked Loops / Phase Lock Loop / Integrated Circuit Design / Integrated Circuit Packaging / Transceivers

Techniques to evolve a C++ based system design language

Object Oriented Programming / Intellectual Property / Microelectronics / System Design / Complex System / Hardware / Process Design / Design Methodology / Data Structures / Chip / System on a Chip / Dynamic System / Object Oriented / Integrated Circuit Design / Hardware / Process Design / Design Methodology / Data Structures / Chip / System on a Chip / Dynamic System / Object Oriented / Integrated Circuit Design

System-Level SRAM Yield Enhancement

Manufacturing / Geometry / Resource description framework / System on Chip / Yield Management / Fluctuations / Logic Design / Subthreshold leakage / Integrated Circuit Design / Threshold Voltage / Fluctuations / Logic Design / Subthreshold leakage / Integrated Circuit Design / Threshold Voltage

A 400-MHz S/390 microprocessor

High Frequency / Fixed Point Theory / Power Supply / Cycle Time / Circuit Design / Logic Design / Floating Point / Timing Optimization / Electrical And Electronic Engineering / Power Dissipation / Phase Lock Loop / Integrated Circuit Design / Logic Design / Floating Point / Timing Optimization / Electrical And Electronic Engineering / Power Dissipation / Phase Lock Loop / Integrated Circuit Design

System-Level SRAM Yield Enhancement

Manufacturing / Geometry / Resource description framework / System on Chip / Yield Management / Fluctuations / Logic Design / Subthreshold leakage / Integrated Circuit Design / Threshold Voltage / Fluctuations / Logic Design / Subthreshold leakage / Integrated Circuit Design / Threshold Voltage

New SRAM design using body bias technique for ultra low power applications

Nanoelectronics / Low Power Electronics / Sram / Application Software / Low voltage / Integrated Circuit Design / Threshold Voltage / Integrated Circuit Design / Threshold Voltage

A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations

Scheduling / VLSI / Very Large Scale Integration / Time Complexity / Circuits / Job shop scheduling / Logic Design / Logic Synthesis / Registers / Process Parameters / Cost Function / Quadratic Programming / Euclidean Distance / Integrated Circuit Design / Job shop scheduling / Logic Design / Logic Synthesis / Registers / Process Parameters / Cost Function / Quadratic Programming / Euclidean Distance / Integrated Circuit Design

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